This invention relates to dynamic random access memory (DRAM) cells and in particular to a DRAM cell which has greatly enhanced storage capacity as well as immunity to alpha particles and which is highly scalable.
In recent years DRAM technology has progressed steadily to the point that 1 Megabit devices are presently mass produced while 4 Mbit and 16 Mbit devices are in advanced stages of development. These DRAM devices all employ a single transistor as a transfer device and a storage capacitor per bit. Each successive generation of DRAM cells has resulted in smaller device geometries, smaller cell sizes, a diminishing storage capacitance, and an increasing number of cells sharing a common bit line. To maintain an acceptable signal-to-noise level, the DRAM industry has focused the majority of its efforts on improving the charge storage efficiency per unit of silicon area for the storage capacitor.
One of the earliest commercial single transistor DRAM cells is shown in cross section in FIG. 1a. Cell 100 is known as a planar cell and includes an MOS transistor having drain 101, source 102, gate 103, and channel region 105. Storage capacitor C is formed between plate 104 and substrate 106 across a thin dielectric layer 109. Adjacent cells are isolated from each other via an isoplanar oxide 107 overlying a channel stop region 108. Each cell 100 in a memory array is uniquely accessed through a bit line 111 connected to drain 101 and an orthogonal word line connected to gate 103. Plate 104 of the storage capacitor is a conductive layer held at a fixed voltage, usually ground or the supply voltage. The cell is written by turning on the transfer transistor and either charging or discharging capacitor C. During reading, the contents of capacitor C is dumped onto the precharged bit line and is sensed at a sense amplifier (not shown) as either a low (if charge flows from the bit line into capacitor C) or as a high (if charge stored on capacitor C flows into the bit line). A high ratio of cell capacitance C to the parasitic capacitance of the bit line is key for the reliable operation of the DRAM cell over a wide range of operating temperatures. Typically, the bit line capacitance should not be more than approximately 15 times the cell capacitance C.
To enhance the storage capacitance C of cell 100, prior art devices have used techniques such as reducing the thickness of storage dielectric 109 to below 10 nanometers or have optimized the surface doping concentration of substrate 106--the so called HIGH-C cell, as described, for example in Chatterjee et al., "A Survey of High Density Dynamic RAM Cell Concepts," IEEE Trans Electron Devices, volume 26, number 6 (June 1979). However, for devices of greater than 1 Mbit, cell 100 and in particular planar capacitor C, are nearing the end of their usefulness due to the inability of a planar structure to provide adequate storage capacitance in an ever decreasing cell area.
A variation of the planar capacitor structure has been proposed by I. Lee et al., "A 64Kb MOS Dynamic RAM," IEEE Digest of Technical Papers from 1979 ISSCC, p. 146. This cell is known as the stacked capacitor cell, and is shown in cross section in FIG. 1b. A similar, more compact stacked capacitor cell has been proposed by M. Koyanagi et al in an article entitled "Novel High Density, Stacked Capacitor MOS RAM," Technical Digest of IEEE 1978 International Electron Devices Meeting, p. 348. Two variations of this cell are shown in cross section in FIGS. 1b and 1c. Cell 200 (FIG. 1b) and cell 300 (FIG. 1c) both have their storage capacitor C implemented across a thin dielectric film 209, 309 sandwiched between two storage electrodes consisting of a bottom plate of N+ doped polysilicon 214, 314 and a top plate of N+ doped polysilicon 204, 304, respectively. The bottom plate is electrically connected to source 202, 302 of the transfer transistor through a buried contact connection 215, 315. The main difference between cell 200 and cell 300 is that the latter folds part of the capacitor back over access gate 303, thereby using a greater part of the total available cell area for storage than the former. Cells 200 and 300 employ thicknesses of between 200 and 500 nanometers for all three polysilicon layers P.sub.1, P.sub.2, and P.sub.3, so as to minimize the metal step coverage problems inherent to a triple polysilicon layer surface topology.
The stacked capacitor cells provide somewhat greater storage efficiency than planar cells. They are also less susceptible to upset from local hits by high energy ionizing particles such as alpha particles. This is because only the relatively small area around junction 202 or 302 can collect charge carriers generated in substrate 213, 313 by an incident high energy particle. In contrast, the planar cell capacitor (FIG. 1a) stores its charge at the surface depletion layer 106 and is therefore quite susceptible to such alpha particle hits.
Despite these advantages the stacked capacitor DRAM cell has not seen wide acceptance. The main reason for this is that the stacked capacitor cell still employs a planar capacitor and therefore has limited scalability as the cell becomes smaller and smaller.
Because of area limitation of the planar and stacked capacitor DRAM cells, a major thrust has been undertaken by DRAM manufacturers to develop a third type of cell--the trench DRAM cell. An example of the simplest of such cells is given in the cross sectional view of FIG. 1d.
The prior art trench DRAM cell 400 of FIG. 1d includes an access transistor consisting of gate 403 which is part of a word line, drain 401 which is part of a bit line, storage node 402, and trench capacitor C which is electrically connected to storage node 402. Trench capacitor C consists of a deep trench etched into the silicon surface with essentially vertical walls 416, N+ diffused silicon region 414 serving as the first electrode of trench capacitor C, dielectric insulation layer 409, and polycrystalline silicon field plate 404 serving as the second electrode of the trench capacitor. The storage capacitance of trench capacitor C can be increased by making the trench deeper. Oxide isolation regions 407 are used to isolate cell 400 from adjacent cells and trenches in a memory array.
There are several other variations of the use of the trench structure for high density DRAM cells. A good review article of the various DRAM cells previously proposed is provided by P. Chatterjee et al., "Trench and Compact Structures for DRAMs", Technical Digests of IEEE International Electron Devices Meeting, December 1986, p. 128.
Although Trench DRAM cells offer much better area storage efficiency than the planar or stacked capacitor cells and are therefore more scalable, they are extremely complicated to manufacture.
An example of an extremely complex trench cell is provided by M. Inoue et al., "A 16 Mbit DRAM with an Open Bit Line Architecture," IEEE 1988 ISSCC Digest of Technical Papers, p. 246 Inoue achieves an exceedingly small cell (1.5 microns.times.2.2 microns=3.3 microns.sup.2) with a rather high storage capacity of 50 femtoFarad by using a narrow trench to completely surround the outer perimeter of the MOS transfer transistor, using the polysilicon plate which fills the trench also to serve as the device isolation area. This type of structure requires that the storage capacitor trench be submerged below the transfer transistor to a depth of more than 3.0 microns below the silicon surface, making the fabrication of this structure extremely difficult, and not realistically practical.
Some of the difficulties which are commonly encountered in forming trench DRAM cells are etch uniformity in etching the deep small diameter cylindrical trench cavities, keeping the inner vertical walls 416 clean from contamination, redeposition of etched material, growing or depositing uniform thin films of high quality dielectrics 409, assuring good vertical conformality of the polycrystalline plate 404, maintaining a flat surface topology and preventing leakage between adjacent trenches. These difficulties will become more severe with future generation trench DRAMs requiring ever deeper trench storage capacitors. For example, in etching 4 million trenches required for a 4 Mbit device, it is impossible to assure that all trenches have been etched to the same depth. Therefore, some memory cells may end up with shallower trenches, resulting in smaller storage capacitors than their neighboring cells.